1. Technical Field
This disclosure relates to semiconductor memories and more particularly, to a hierarchical prefetch method and apparatus for increasing overall data rate or bandwith for semiconductor memories.
2. Description of the Related Art
Dynamic Random Access Memory (DRAM) is utilized in various electronic systems for storing large amounts of digitally encoded information. The data rate of DRAMs have become more critical since microprocessors are operating at ever increasing clock speeds. This requires DRAM devices to have much faster data rates for both reading and writing functions to keep pace with the microprocessors. The data rate of the DRAM is limited by the access speed from the address input to data input/output, which requires a signal travel along a number of circuits, a receiver, a driver, a decoder and sense amplifier. This access speed is not easy to improve upon without improving the process technology to a faster device speed.
A number of techniques have therefore been developed to increase the data rate with circuit technologies. One such technique is known as "pre-fetching", which is disclosed in U.S. Pat. No. 5,285,421, entitled SCHEME FOR ELIMINATING PAGE BOUNDARY LIMITATION ON INITIAL ACCESS OF A SERIAL CONTIGUOUS ACCESS MEMORY, issued on Feb. 8, 1994 and U.S. Patent No. 5,392,239 to Margulis et al., entitled BURST MODE DRAM, issued on Feb. 21, 1995.
The "pre-fetching" technique takes advantage of the burst access pattern by latching additional data for the subsequent burst pattern into a register, in addition to the data corresponding to the specified address. The "prefetching" technique, more particularly receives an initial address and subsequent addresses are generated internally within a DRAM. The internal address generation is much faster than receiving subsequent addresses externally, substantially improving the access of the subsequent burst pattern if the subsequent data are available. By storing the additional data fetched in the register as a prefetch, subsequent data may be accessed in the time the subsequent address is generated. Thus, the total time for completing a number of sequential accesses is reduced, improving the data rate of the burst access patterns as large as the number of the prefetch.
The data rate of 200 Mb/sec or beyond is realized for a 256 Mb DRAM with 2-bit prefetch. The prior art includes a DQ block (input/output pins) where 2 Read/Write Driver's (RWDs) bus lines are steered into each DQ. This improves a data rate as fast as two times the data rate without prefetching. Increases in prefetch, however, come at a high cost to chip size overhead.
Therefore, a need exists for a hierarchical prefetch method and apparatus for increasing data rate or bandwith while maintaining low chip size overhead for semiconductor memories.